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#power#performance#more#data#faster#speed#gpu#idle#cards#cpu

Discussion (52 Comments)Read Original on HackerNews

dan_sblabout 22 hours ago
> For example, when the GPU is fully idle, nvidia-smi tells me that it’s only pulling 88W of power.

I haven't used a non-laptop GPU in some time, but that is a crazy amount of "idle" power consumption. Is this normal for cards like this?

Aurornisabout 22 hours ago
Server cards are not optimized for idle power usage. They’re expected to be fully utilized.

For server gear it’s more common to have less dynamic power and voltage switching because it produces more predictable performance and latency.

cmovqabout 22 hours ago
For GeForce cards you can get similar behavior by setting “Prefer maximum performance” which disables some of the low power states.
UltraSaneabout 7 hours ago
CPU sleep states are normally disabled on servers because CPU demand can increase faster than the CPU speed can increase. It is much better to have a $20,000 CPU running at max MHz at all times.
wildzzzabout 22 hours ago
If my gpu is sitting idle, and I mean idle with nothing loaded into its memory, it's sitting at about 18W. If I load in model that uses nearly all of the memory but that model is idle, it's at 36W. If that model is actively thinking, it's like 118W. I think this is likely due to the GPU being aware that there is real data loaded into memory and turning up the DRAM refresh rate whereas when nothing is loaded, the dynamic power is as low as possible.
legitronicsabout 20 hours ago
Yes, I have some of these cards and AFAICT the HBM2e chips just always run at full speed. I have different variants of the pcie cards and while I can get the gpu itself into a lower power state the memory just runs full tilt. Though I see 40w on my “normal” cards and 60w on the Frankenstein card that thinks it’s an sxm4.
monster_truckabout 15 hours ago
IIRC this was one of the issues with 2/2e, some combination of the various available memory controllers not agreeing on a standard to manage timings and power states. I haven't played around with my Radeon VII in a long while now.

That aside idle power consumption is a driver-to-driver affair from both amd and novideo, sometimes I'm only pulling 15-30W when nothing is happening and other times it decides it needs 110w for a static 500hz screen

umanwizardabout 21 hours ago
I suspect the act of running nvidia-smi itself prevents the GPU from being put into a low-power state.
zacmpsabout 21 hours ago
From memory this is true and nvml (Nvidia management library) is the way to get stats that doesn't cause the GPU to wake.
nzachabout 23 hours ago
I went in expecting to find 'branch prediction'[0] as the answer, but apparently things are even more complex nowadays.

[0] - https://stackoverflow.com/questions/11227809/why-is-conditio...

DavidVoidabout 16 hours ago
I don't think GPUs ever had branch prediction in the first place. You can however run into poor performance due to thread divergence, which is a similar kind of issue (with much less black magic).
gruezabout 22 hours ago
>I went in expecting to find 'branch prediction'[0]

GPUs do branch prediction? I thought they didn't bother and try to minimize wasted effort by using high amounts of concurrent threads?

jayd16about 22 hours ago
They do texture prefetching, which is sorta similar.
kangaliooabout 23 hours ago
To be fair, the culprit in the article is _less complex_ than branch prediction: "with random data, bits are flipped often, and bit flips in transistors inherently draw power" is less mental gymnastics than "with random data, the cpu fails to predict the future, causing redundant speculative execution"
eff-nixabout 18 hours ago
But why do we expect random data to result in more bit flips? That seems harder to argue than the mechanics of a basic branch prediction system.
atq2119about 14 hours ago
Think about it from the other end. Why would any bits flip at all in the data path of your matrix multiplier when all the matrices are 0?
bee_riderabout 21 hours ago
I expected a “torch is smart enough to keep track of cases where it just initialized the C in C <= A*B+C to zero, avoiding the add” type situation but I was wrong.
ryanisnanabout 21 hours ago
That's exactly what I thought.
ggambettaabout 21 hours ago
I'd have guessed multiply-by-0 and multiply-by-1 can be special-cased to run much faster and simpler code paths, like you'd do when writing MUL for a processor that doesn't have it (I <3 z80)
Thorondorabout 20 hours ago
Hardware engineer here. Special casing the multiply by 0 and multiply by 1 paths is harder than it sounds. In software, the cost of adding special cases is simply performance. You're adding more instructions that execute in sequence on a CPU that already physically exists. Doing this for your multiply case is worthwhile because the speedup is large for 0 and 1 while the cost is not that large (relative to the time taken for the whole multiplication operation) for other values.

Hardware is different. Every operation that can be performed in hardware by a chip needs dedicated circuitry. Special casing 0 and 1 means adding at least OR reduction on each operand and a dedicated multiplexer for every bit of the output. Those transistors use power even when they're not in use (leakage power is a huge issue on modern semiconductor processes). They also degrade timing by adding more gates on critical paths through the multipliers. (The timing issue here is that all operations that happen between one flip-flop and another flip-flop need to finish within one clock cycle.) And unless there are whole blocks of 0's and 1's (this does happen in certain neural networks), you typically won't see a direct speedup anyway. In software terms, the matrix multiply is scheduled as many parallel operations that cannot be accelerated much overall by skipping a few operations in some "threads."

All of this makes zero skipping a nontrivial topic. People do still try to do it but it needs serious consideration as, depending on the application, the case is rarely one-sided.

ggambettaabout 2 hours ago
Thanks for the detailed explanation, I had no idea about any of this.
nomelabout 19 hours ago
You didn't touch on the most important aspect for cost: die area!

How much die space ($) will that circuitry, that's probably statistically near zero chance for you main customers workload (who has model weight of 0 or 1!?), add. And, if you can stomach the cost, what else could you put there instead?

Thorondorabout 18 hours ago
Weights should not be 0 (at least not frequently) but in a ReLU-based neural network, activations are 0 pretty often. You're absolutely right about die area though.
rowanG077about 1 hour ago
I expect the degraded critical path will most likely be worse than a bit of die area. On modern processes you have A LOT of transistors to play with.
imtringuedabout 2 hours ago
Nvidia has added structural sparsity to their GPUs and every time they pull out a flops or tops number, they assume you will use structural sparsity.

The die area argument here makes no sense. Supporting structural sparsity can be done either by duplicating the multipliers with and without the support or you have a single general purpose multiplier that does both, in which case you can have twice as many of them.

Also, in ReLU^2 networks, 90%+ parameters are zero.

jayd16about 23 hours ago
I can't tell from the blog, is this actually verified or is it theory and then numbers showing plausibility?

I could certainly come up with alternative theories about memory compression and prefetching if we were talking about texture reads.

saagarjhaabout 12 hours ago
It’s real, you can measure it yourself on modern Nvidia hardware
jetsamflotsamabout 21 hours ago
I feel like many of the comments missed the point or didn't read the article. What I believe this article is stating (and I've read this many times during my PhD for various reasons), is that the input data distributions affect how many transistor state changes there are during multiplication. Since these events are a large portion of energy loss/heat generation, the clocks won't be throttled as much for certain data patterns.

There was a workshop paper from SC24 that did more experiments around this I believe. I can't find it now though.

ameliusabout 22 hours ago
Sounds like a side channel attack waiting to happen.
unglaublichabout 22 hours ago
So I guess we'll all be applying a random rotation to our matrices now to obscure their contents, like TurboQuant does. https://arkaung.github.io/interactive-turboquant/#rotation
buildbotabout 22 hours ago
Not that it super matters, but random hadamards for quantization have been a thing since way before turboquant.

https://arxiv.org/abs/2404.00456

DiabloD3about 18 hours ago
Which llama.cpp now does.
b0r3dthisD4yabout 15 hours ago
Yeah I am willing to drive faster down a straight flat runway as others ahead of me give an all clear.

When you make it so the computer does not have to compute all possible states of matter it finishes faster.

gdevenyi1 day ago
People have been noticing the effects of this in local LLM inference. Power limiting seems to improve overall performance!
Aurornisabout 23 hours ago
This is not observable from LLM inference, where you would not encounter uniform matrices.

Power limiting does not improve performance but it does improve efficiency. You might be able to get 90% of the performance for only 70% of the power usage, for example. It does not make the card go faster though.

Lercabout 22 hours ago
When thermal throttling occurs you can perform faster by running slower.

This is precicely because of the efficiency. The lower efficiency of the higher speed triggers a much lower performance sooner.

Aurornisabout 21 hours ago
> When thermal throttling occurs you can perform faster by running slower.

This is not true unless the throttling algorithm is so broken that it's oscillating between extremes.

The parts have a curve of clock speed versus voltage. More clock speed means higher performance. That goes further up the voltage curve, meaning more power.

Throttling just moves the card further down the voltage to clock speed curve. It reduces clock speed, reducing performance.

The cards don't "perform faster by running slower". If you run the card slower, it performs slower.

gchamonlive1 day ago
In general, constraints require optimizations and rearchitectures. I'd also expect the ram shortage for instance to have a big impact on the software industry as a whole, specially in games. They will need to make do with what people have, a ps5/pro or similar in PC power.
aNoob7000about 24 hours ago
I actually think it is a good thing to introduce constraints to AI and the overall tech industry. Hopefully everyone will have to look at improving performance without having to add RAM or increase CPU/GPU performance.
gchamonliveabout 22 hours ago
As long as these constraints are for everyone and not just for thee and not for me, and become an instrument for big tech to keep consumers dependent on their infra.
bitwizeabout 22 hours ago
It wouldn't surprise me to see some ML algorithm in silico somewhere to select faster matmul paths on favorable data. Yo dawg, I heard you like AI, so we put some AI in your AI so you can infer while you're inferring.
rowanG077about 1 hour ago
This is old news. AMD was this in their CPUs years ago.
Nevermarkabout 22 hours ago
Here is one: An adjustment to weight updates, that makes it more likely for weights to stay uniformly distributed.

~257.5 teraflops for normal distribution, versus ~268 teraflops uniform, reported on the first graph.

I would have liked to see a straight graph of performance vs. clock speed, for each type of data. Pick your data statistics, then pick the peak performance clock speed accordingly.

And for actual runs, from a pre-run sampled curve.

falcor84about 22 hours ago
And there's at least one more level of inception at the data center level, where they use AI to optimize power usage (particularly by predictively controlling cooling, and adaptively rescheduling tasks).
evanjrowleyabout 23 hours ago